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RC5060
ACPI Switch Controller
Features
Implements ACPI control with PWROK, SLP_S3# and SLP_S5# Switch and linear regulator controller for 3.3V Dual (PCI) Linear regulator controller and linear regulator for 2.5V Dual (RAMBUS) Two switch controller for 5V Dual (USB) Switch controller and linear regulator for 3.3V SDRAM Provides SDRAM and RAMBUS power simultaneously Adaptive Break-before-Make Integrated Power Good Drives all N-Channel MOSFETs plus NPN Latched overcurrent protection for outputs Power-up softstarts for the linear regulators UVLO guarantees correct operation for all conditions 20 pin SOIC package
Applications
Camino Platform ACPI Controller Whitney Platform ACPI Controller Tehama Platform ACPI Controller
Description
The RC5060 is an ACPI Switch Controller for the Camino, Whitney and Tehama Platforms. It is controlled by PWROK, SLP_S3# and SLP_S5#, and provides 3.3V Dual for PCI, 3.3V for SDRAM, 2.5V Dual for RAMBUS, and 5V Dual voltages. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5060 also offers integrated Power Good and Current Limiting that protects each output, and softstart for the linear regulators. The RC5060 is available in a 20 pin SOIC.
Block Diagram
+5V Standby PWROK 3.3V Main 3 +5V Main 4 3.3V SDRAM 13 9 PWRGD Over Current +3.3V Main 3.3V MAIN 16 Over Current + REF + 14 + + REF 7 8 +3.3V Dual (PCI) 6 +5V Standby Softstart + + Over Current Ref + 19 Osc 18 17 REF +5V Dual (USB) +5V Standby 12 SLP_S3# 10 SLP_S5# 11 5 1 2 20 +12V
15 2.5V Dual (RAMBUS)
REF
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RC5060
PRODUCT SPECIFICATION
Pin Assignments
QCAP PUMP SDRAMOUT SDRAMFB 5VSTBY 3VOUT1 3VOUT2 3VFB PWRGD SLP_S3# 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCP 5VOUT1 5VOUT2 5VFB RAMBUSOUT RAMBUSFB GND SS PWROK SLP_S5#
RC5060
Pin Definitions
Pin Number 1 2 3 4 Pin Name QCAP PUMP SDRAMOUT SDRAMFB Pin Function Description Charge pump cap. Attach flying capacitor between this pin and PUMP to generate high voltage from standby power. Charge pump switcher. 3.3V SDRAM gate control. Attach this pin to a transistor powering 3.3V SDRAM from the 3.3V main supply. 3.3V SDRAM voltage feedback. Pin 4 is used as the input for the voltage feedback control loop for 3.3V SDRAM, and also sources 3.3V SDRAM in standby. 5V Standby. Apply +5V standby on this pin to run the circuit in standby mode. 3.3V main gate control. Attach this pin to a transistor powering 3.3V dual from the 3.3V main supply. 3.3V standby gate control. Attach this pin to a transistor powering 3.3V dual from the 5V standby supply. 3.3V voltage Feedback. Pin 8 is used as the input for the voltage feedback control loop for 3.3V dual. Power Good. Open collector output is high when all outputs are valid. SLP_S3#. Control signal governing the Soft Off state S3. Internal current source pulls this line high if left open. SLP_S5#. Control signal governing the Soft Off state S5. Internal current source pulls this line high if left open. PWROK. Control signal for switches. Internal current source pulls this line high if left open. Softstart. Attach a capacitor to this pin to determine the softstart rate. Ground. Connect this pin to ground. 2.5V feedback. Pin 15 is used as the input for the voltage feedback control loop for 2.5V dual (RAMBUS), and also sources 2.5V dual in standby. 2.5V base drive control. Attach this pin to an NPN transistor powering 2.5V dual (RAMBUS) from the 3.3V main supply. 5V Voltage Feedback. Pin 17 is used to sense undervoltage to protect the 5V dual from overcurrent. 5V standby gate control. Attach this pin to a transistor powering 5V dual from the 5V standby supply. 5V main gate control. Attach this pin to a transistor powering 5V dual from the 5V main supply. Main Power. Apply +12V through a diode on this pin to run the circuit in normal mode. Bypass with a 0.1F capacitor. When 12V is not present, this pin produces voltage doubled 5V standby.
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5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5VSTBY 3VOUT1 3VOUT2 3VFB PWRGD SLP_S3# SLP_S5# PWROK SS GND RAMBUSFB RAMBUSOUT 5VFB 5VOUT2 5VOUT1 VCCP
2
PRODUCT SPECIFICATION
RC5060
Absolute Maximum Ratings
VCCP All Other Pins Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Thermal Resistance Junction to Ambient JA Thermal Resistance Junction-to-case, JC 15V 13.5V 150C -65 to 150C 300C 85C/W 24C/W
Recommended Operating Conditions
Parameter +3.3VMAIN +5VMAIN +5VSTBY +12V Ambient Operating Temperature Conditions Min. 3.135 4.75 4.75 11.4 0 Typ. 3.3 5 5 12 Max. 3.465 5.25 5.25 12.6 70 Units V V V V C
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RC5060
PRODUCT SPECIFICATION
Electrical Specifications
(V+5VSTBY = V+5VMAIN =5V, V+3.3V = 3.3V, V+12V = 12V and TA = +25C using circuit in Figure 4, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter +5V DUAL VOut1, On VOut1, Off VGS, Out2 VOut2, Off Maximum Drive Current, Each Overcurrent Limit: Undervoltage Overcurrent Delay Time Output Driver Overlap Time +3.3V DUAL VOut1, On VOut1, Off VOut2, On Total Output Voltage Variation1 Maximum Drive Current Minimum Load Current Overcurrent Limit: Undervoltage Overcurrent Delay Time Output Driver Deadtime +2.5V DUAL IB, On IOut Total Output Voltage Variation1 Overcurrent Limit Overcurrent Delay Time Output Driver Overlap Time +3.3V SDRAM Vout, On Vout, Off IOut Overcurrent Limit Total Output Voltage Variation1 Overcurrent Delay Time Output Driver Dead Time Common Functions PWRGD Threshold PWRGD Delay Time PWRGD Sink Current Charge Pump Frequency +5VSTBY UVLO * 1 250 4.5 80 150 %Vout sec mA KHz V * 200 SDRAMFB On * 3.135 I = 10A SDRAMOUT Off * * * 100 80 3.3 150 1500 3.465 10 200 V mV mA %Vout V sec nsec See Figure 2 * 1 RAMBUSOUT On RAMBUSOUT Off * * * 200 144 2.375 2.5 80 150 5 2.625 mA mA V %Vout sec sec See Figure 2: Main Standby : Standby Main * * 2 200 I = 10A Standby 3VOUT2 On 3VOUT1 On 3VOUT2 On * * * * * * 80 150 6 1000 5 3.135 90 50 3.3 3.465 10 200 V mV mA V mA mA %Vout sec sec nsec See Figure 2 * 1 I = 10A Standby I = 10A * * * * * 10 80 150 5 2.7 200 10 200 V mV V mV mA %Vout sec sec Conditions Min. Typ. Max. Units
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PRODUCT SPECIFICATION
RC5060
Electrical Specifications (continued)
(V+5VSTBY = V+5VMAIN =5V, V+3.3V = 3.3V, V+12V = 12V and TA = +25C using circuit in Figure 4, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter +5VSTBY UVLO Hysteresis +12V UVLO +12V UVLO Hysteresis +5VSTBY Current +12V Current Input Logic HIGH Input Logic LOW Softstart Current Control Line Input Current Over Temperature Shutdown
Note: 1. Voltage Regulation includes Initial Voltage Setpoint and Output Temperature Drift.
Conditions
Min.
Typ. 0.5 7.5 1
Max.
Units V V V
MAIN Power Present * * 3 SLP_S5#, SLP_S3#, PWROK * 2.0
10 2.5
25 10 0.8
mA mA V V A A C
6 150
9 10
Table 1. Power Descriptors
PWROK SLP_S3# SLP_S5# Main 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 01 ON OFF OFF OFF OFF OFF OFF ON OFF 5V/3.3V Duals ON, Powered from STANDBY ON, Powered from STANDBY ON, Powered from STANDBY ON, Powered from STANDBY ON, Powered from STANDBY ON, Powered from STANDBY ON, Powered from STANDBY 2.5V RAMBUS/ 3.3V SDRAM ON, Powered from STANDBY ON, Powered from STANDBY ON, Powered from STANDBY OFF OFF OFF State S0 S3 S3 S3 S5 S5 S5 S5 S5* Usage S0 S0 S3 S3 S3 S0 S0 S5 S5 S5 S0 Not Used *
ON, Powered from MAIN ON, Powered from MAIN
ON, Powered from MAIN OFF OFF
*When PWROK = SLP_S3# = 0 and SLP_S5# transitions from 0 to 1, the RC5060 remains in the S5 state. See Table 2.
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RC5060
PRODUCT SPECIFICATION
101
111 S0
001 S3 Blocked 011 100
000 S5
110 Not Used
010
Figure 1. Power State Usage Diagram
Table 2. State Transition Table
Final Control Signal
000 000
Initial Control Signal
001 x -- x -- x -- x S3
010 S5 S5 -- S5 -- S5
011 x x -- x -- x S3
100 -- S5 -- S5 -- S5 -- S5
101 x -- x -- x -- x S3
110 -- S5 -- S5 -- S5 -- S5
111 S0 S0 S0 S0 S0 S0 S0 --
-- S5 -- S5 -- S5 -- S5
001 010 011 100 101 110 111
Notes: 1. Control Signal order: PWROK, SLP_S3#, SLP_S5# 2. Dash (--) signifies that no state change takes place. 3. X signifies that the state transition is blocked, and the RC5060 remains in the S5 state.
OUTPUT 1 2V 2V tDT 2V OUTPUT2 2V tOT 2V 2V 2V tOT
OUTPUT1
tDT 2V
OUTPUT2
Figure 2. Deadtime and Overlap Time Measurements
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PRODUCT SPECIFICATION
RC5060
STBY SLP_S3# PWROK MAIN MAIN
STBY
SLP_S3# PWROK
SLP_S5# DUAL MEMORY
Figure 3. Control Logic for Dual Voltages and Memory Voltages
Application Circuits
+5V Standby 5V Main +12V 3.3V Main
D1
PWRGD
R1
C1 C3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
C2 C9 Q5 Q6
+5V Dual
Q1
Q3 Q4
U1 RC5060
Q2
C10
C7
C8
2.5V Dual (RAMBUS) 3.3V SDRAM 3.3V Dual (PCI)
SLP_S5# PWROK SLP_S3#
C5
C6
C4
Figure 4. Camino ACPI Selector
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PRODUCT SPECIFICATION
RC5060
Table 3. RC5060 Application Bill of Materials for Camino
Reference C1-3, C8 C4-6, C9 C7 C10 R1 D1 Q1, Q3 Q2 Q4 Q5-6 U1 Manufacturer, Part # Various Various Various Various Various Fairchild MBR0520L Fairchild FDS4410DY Fairchild TIP41A Fairchild FDS6630A Fairchild NDH833N Fairchild RC5060 Quantity 4 4 1 1 1 1 2 1 1 2 1 Description 100nF, 25V 220F, 6V 100nF, 50V 47F, 10V 10K Resistor 20V, 1/2A Schottky N-channel MOSFET NPN N-channel MOSFET N-channel MOSFET ACPI Switch Controller Rds,on = 20m @ Vgs = 4.5V VCE ~0.4V @ IC = 2A, IB = 100mA SO-8 Rds,on = 25m @ Vgs = 2.7V Ceramic Tantalum, ESR ~ 0.1 Ceramic Tantalum Comments
+5V Standby 5V Main +12V 3.3V Main
D1
PWRGD
R1
C1 C3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
C2
C9
Q5 Q6
+5V Dual
Q1
Q3 Q4
U1 RC5060
C7
C8
C10
3.3V SDRAM 3.3V Dual (PCI) SLP_S5# PWROK SLPS3#
C5
C4
Figure 5. Whitney ACPI Selector
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PRODUCT SPECIFICATION
RC5060
Table 4. RC5060 Application Bill of Materials for Whitney
Reference C1-3, C8 C4-5, C9 C7 C10 R1 D1 Q1, Q3 Q4 Q5-6 U1 Manufacturer, Part # Various Various Various Various Various Fairchild MBR0520L Fairchild FDS4410DY Fairchild FDS6630A Fairchild NDH833N Fairchild RC5060 Quantity 4 3 1 1 1 1 2 1 2 1 Description 100nF, 25V 220F, 6V 100nF, 50V 47F, 10V 10K Resistor 20V, 1/2A Schottky N-channel MOSFET N-channel MOSFET N-channel MOSFET ACPI Switch Controller Rds,on = 20m @ Vgs = 4.5V SO-8 Rds,on = 25m @ Vgs = 2.7V Ceramic Tantalum, ESR ~ 0.1 Ceramic Tantalum Comments
Vcore 2V/17.4A ATX 5Vmain, 18A RC5058 SO24 5Vstdby 720mA Typedet Synchronous Conversion Vnb 1.8V/2A Linear Linear/Switch Vck 2.5V/600mA Linear Switch Switch RC1587 Vtt 1.5V/2A Vagp 3.3V/1.5V/2A
12V, 6A
5Vdual 1A/1A/200mA USB
3.3Vmain, 14A RC5060 SO20 Linear Switch Linear PWROK SLP_S3# SLP_S5# Linear 2.5V RAMBUS @ 2A/144mA 3.3Vdual 2.4A/500mA/500mA PCI
Linear Switch
3.3V SDRAM @ 4.8A/100mA
Figure 6. Camino System Architectural Block Diagram (Power Paths Only)
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RC5060
PRODUCT SPECIFICATION
Application Information
The RC5060 Controller
The RC5060 is a fully compliant ACPI controller IC. Used with an ATX power supply, it generates a 5V Dual voltage, a 3.3V Dual for PCI, and power for both SDRAM and RAMBUS, and has a large array of additional protection functions integrated in. Used in conjunction with Fairchild's RC5058, it provides the complete set of control and power functions necessary to implement a Camino or Whitney motherboard. It can also be used to generate the dual voltages necessary for a Tehama motherboard.
S5 is a state in which memory is off, and the last state of the processor has been written to the hard disk. Since the disk is slow, the computer takes longer to come back to full operation. However, since memory is off, this state draws minimal power. It is anticipated that only the following state transitions will occur: S0 S3, S0 S5, S3 S5, S5 S0, and S3 S0; the transition S5 S3 will occur only as an intermediate state during the transition from S5 S0. To prevent overcurrent limit from activating, the RC5060 blocks this transition. For example, when PWROK = SLP_S3# = 0, and SLP_S5# transitions from 0 to 1, the RC5060 remains in the S5 state. See Table 2.
Overview of ACPI
The Advanced Configuration and Power Interface, or ACPI, is a system for controlling the use of power in a computer. It enables the computer manufacturer and the computer user to determine the computer's power usage dynamically. For example, when the computer has been unused for a certain time, the monitor and peripherals could be turned off, and their states saved to memory. After a longer period, the processor could be turned off, and the memory saved to disk. A peripheral could then re-awaken the entire system on the occurrence of an event, such as the arrival of a FAX on a modem. As shown in Figure 6, the available power inputs to the computer system from the ATX power supply are +5V main, +12V main, +3.3V main, and +5V standby. "Main" means that these power outputs are available under full-power operation of the system, but can be turned off in some of the powersaving modes. "Standby" means that this power output is always present. The most general ACPI system requires four dual outputs: 5V dual, 3.3V dual, 3.3V SDRAM, and 2.5V RAMBUS (or 2.5V dual). "Dual" means that the power can be (but is not necessarily) present whether the main power supplies are present or not. To ensure the presence of these outputs, while not overloading the standby power, they have dual inputs, from both main power and standby. The presence or absence of the dual outputs is determined by the control signals to the RC5060.
5V Dual Output
The RC5060 controls four separate dual outputs, the first of which is the 5V dual. This output is intended to run subsystems such as the USB ports. A typical application that would require the use of 5V dual rather than +5V main for a USB port would be the use of a USB mouse: if the system needs to be able to awaken from sleep when the mouse is moved, then the mouse must be powered from dual, because main power is off. 5V dual is generated by two MOSFET switches, one from +5V main, the other from +5V standby, as shown in Figures 4 or 5. When main power is present, the first switch is on and the second off, and the opposite when main power is absent. Note carefully the polarity of the MOSFET Q5 that delivers power from the +5V main to the 5V dual: opposite to the connection of Q6, the source is connected to the +5V main input, and the drain is connected to the 5V dual output. This connection must be done this way because of Q5's body diode. When +5V main is not present, 5V dual is still on, and if Q5 were connected with the same polarity as Q6, the dual voltage would conduct through the body diode of Q5, attempting to power up the entire +5V main line. It is to avoid this overload that Q5 must be connected as shown. The state of the switches is controlled by the SLP_ S3# and PWROK lines, as shown in Figure 3. When both SLP_ S3# and PWROK are asserted, the main switch is on, and the standby switch is off. If either line is de-asserted, the main switch is off and the standby switch is on. Note that Q5 and Q6 should be low-gate-voltage type MOSFETs, with guaranteed operation at 2.7V Vgs, in order to ensure full enhancement in worst case. In a typical system, it is anticipated that full-power current will be about 1A maximum, and standby current will be about 200mA maximum.
ACPI States
As shown in Table 1, there are three ACPI states that are of primary concern to the system designer, designated S0, S3 and S5. S0 is the full-power state, the state of the computer when it is being actively used. The other two states are sleep states, reflecting differing levels of power-down. S3 is a state in which the processor is powered down, but its last state is being preserved in IC memory, which is kept on. Since memory is fast, the computer can quickly come back up to full operation. However, this state continues to draw moderate power, due to the memory being kept alive.
3.3V Dual Output
The 3.3V dual output is intended to power subsystems such as the computer's PCI slots. A typical application that would require the use of 3.3V dual rather than +3.3V main for a PCI slot would be the use of a modem: if the system needs to be
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PRODUCT SPECIFICATION
RC5060
able to awaken from sleep when the modem receives incoming data, then that slot must be powered from dual, because main power is off. Other slots not requiring dual power can be configured using the control signals. 3.3V dual is generated by two MOSFETs, one from +3.3V main, the other from +5V standby, as shown in Figures 4 or 5. When main power is present, the MOSFET Q3 is turned on as a switch, so that input and output are connected together. When main power is absent, the MOSFET Q4 is controlled by the RC5060 as a linear regulator, generating a regulated 3.3V from +5V standby. As with the 5V dual, the MOSFET Q3 must be connected as shown in the figures, to avoid back-feed. The state of the MOSFETs is controlled by the SLP_S3# and PWROK lines, as shown in Figure 3. When both SLP_S3# and PWROK are asserted, the main switch is on, and the linear regulator is off. If either line is de-asserted, the main switch is off and the linear regulator is on. Q3 and Q4 as shown in Tables 3 or 4 have different RDS,on ratings. In a typical system, it is anticipated that full-power current will be about 2.4A maximum, and standby current will be about 500mA maximum. The difference in maximum currents means that Q4 can be a less expensive device than Q3. The design of the linear regulator for the 3.3V Dual necessitates a minimum load current of 50mA. Furthermore, in order to guarantee stable operation, the output capacitor on the 3.3V Dual must have a minimum ESR as shown in Figure 7. The hatched region shows acceptable values of ESR vs. output capacitance. Values of the output capacitor less than 47F or greater than 300F are not recommended.
300
3.3V SDRAM is generated by one external MOSFET switch from +3.3V main, and one linear regulator internal to the RC5060 from +5V standby, as shown in Figures 4 or 5, and in the block diagram on the front page. When main power is present, the MOSFET Ql is turned on as a switch, so that input and output are connected together. When main power is absent, the internal linear regulator is on, generating a regulated 3.3V from +5V standby. As with the other duals, the MOSFET Ql must be connected as shown in the figures, to avoid back-feed. The state of the external MOSFET and the internal linear regulator is controlled by the SLP_S3# and PWROK lines, and additionally the SLP_S5# line, as shown in Figure 3. When SLP_S5# is de-asserted, both the external MOSFET and the internal linear regulator are off, and there is no output voltage on the 3.3V SDRAM line. If the SLP_S5# line is asserted, the 3.3V SDRAM output is on. In this condition, if either the SLP_S3# or the PWROK line, or both, are de-asserted, the linear regulator is on and the MOSFET is off. Only in the case if both the SLP_S3# and the PWROK lines are asserted, the MOSFET is on and the linear regulator is off. In a typical system, it is anticipated that standby current will be about 100mA maximum. Full power current will be as high as 4.8A maximum, so that Ql must have a low RDS,on in order to prevent excessive voltage drop across it.
2.5V Dual Output
The 2.5V dual output is intended to provide power to RAMBUS memory. Only high-end systems will use this power. Those systems using RAMBUS may also use the SDRAM power, possibly piped to the same slots, to ensure backward compatibility or even mixed operation of SDRAM with RAMBUS. 2.5V dual is generated by one external NPN bipolar acting as a linear regulator from +3.3V main, and one linear regulator internal to the RC5060 from +5V standby, as shown in Figure 4, and in the block diagram on the front page. When main power is present, the NPN Q2 linear regulates, and when main power is absent, the internal linear regulator is on. Q2 cannot be substituted with a MOSFET. If used in one direction, the MOSFET's body diode would permit backfeed; if used in the other direction, it would short-circuit the linear regulator action. 2.5V dual output is controlled in the same way and by the same lines as the 3.3V SDRAM output. In a typical system, it is anticipated that standby current will be a maximum of 144mA, and full-power current may be as high as 2A. This places some significant constraints on the selection of Q2. Since its input may be as low as (3.3V - 5%) = 3.135V, there is only 3.135V -2.5V = 635mV of VCE headroom for its
200 ESR (m) 100
47
100
200 C (F)
300 330
400
Figure 7. Recommended C vs. ESR for Stable Operation of the 3.3V Dual
3.3V SDRAM Output
3.3V SDRAM output is intended to provide power to SDRAM memory. Most systems will use this power. Those systems using RAMBUS may also use the SDRAM power, possibly piped to the same slots, to ensure backward compatibility or even mixed operation of SDRAM with RAMBUS.
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RC5060
PRODUCT SPECIFICATION
operation as a linear regulator. For this reason the RC5060 can provide up to 200mA of steady-state base current. The TIP41A device shown has a sufficiently low VCE, sat to guarantee worst-case regulation even at 2A IE with this base current.
Softstart
Pin 13 of the RC5060 functions as a softstart. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly ramping up the voltage. This ramp in turn controls the internal reference of the RC5060. providing a softstart for the linear regulators. The actual state of the RC5060 on power up will be determined by the state of its control lines. The switches in the system must be either on or off, and so softstart has no effect on their characteristics: if the appropriate control signals are asserted, they will turn on at once. The softstart is effective only during power on. During a transition between states, such as from S5 S0, the linear regulators are not softstarted. It is important to note that the softstart pin is not an enable; pulling it low will not necessarily turn off all outputs.
RC5060 ACPI Control Lines
As already discussed, the RC5060 outputs are controlled by the three ACPI control lines, SLP_S3#, SLP_S5# and PWROK, as summarized in Tables 1 and 2. System designers must in particular be careful to ensure that their system is designed with SLP_S5#, not SLP_S5; if SLP_S5 is used, it must be inverted before being used with the RC5060. The control lines have internal pull-ups of approximately 10A, and so can be controlled by open collector drivers if desired. In a noisy system, it may be desirable to filter these lines, which can be done with a 1K resistor and a small capacitor.
RC5060 Dynamic Operation
The RC5060 is designed to minimize the output capacitance required to hold up the various output lines during transitions between different states. Thus in particular, the 5V dual and 2.5V dual outputs have guaranteed minimum overlap times, the time (as shown in Figure 2) during a state transition during which both main and standby are connected to the output. This overlap time guarantees that a power source is always connected to the output, so that there will be no dip in the output voltage during state transitions. There is also a maximum overlap time, to ensure that the standby power doesn't have to source main power very long, thus minimizing thermal stress on the standby device. The 3.3V dual and 3.3V SDRAM are different than the other outputs, because they are powered by both a linear regulator and a switch. If the linear regulator were to turn on while the switch is on (or vice versa) the linear regulator would supply power to the main line through the switch. For this reason, the linear regulator must be off before the switch is on, and vice versa. Thus, these two outputs have guaranteed minimum deadtime when both linear regulator and switch are off. During this time, the output capacitors must hold up the load, and so there is also a specified maximum deadtime, allowing a maximum necessary capacitance to be selected, see below.
Charge Pump
In main power operation, the RC5060 is run from the +12V main supply. This supply also provides voltage to the various MOSFET gates. However, during standby, this supply is off. To provide power to the chip and the appropriate gates, the RC5060 incorporates a free-running charge pump. As shown in Figures 4 and 5, and in the block diagram on the front page, a capacitor attached between pins 1 and 2 of the RC5060 acts as a charge pump with internal diodes. The charge pump output is internally diode or'red with the 12V input. The 12V input must have a series diode to prevent back-feeding the charge pump to the + 12V main when in standby. The 12V input line needs a bypass capacitor for high-frequency noise rejection.
Overcurrent
The RC5060 does not directly detect current through the eight devices that power its outputs. Instead, it monitors the four output voltages. In the event of a hard short, the voltage drops below 80% of nominal, and all outputs are latched off, and remain off until 5V standby power is recycled. The overcurrent latch off is delayed by 150sec to prevent nuisance trips. In the S5 state, when the memory outputs are off, the voltage monitors on the memory lines are disabled, to prevent tripping the overcurrent. When turning these lines back on from the S5 state, overcurrent is prevented from tripping because the S3 state is blocked. See Table 2. If the 2.5V dual is not used, its feedback line, pin 15, must be connected to 5V dual as shown in Figure 5, to prevent an overcurrent trip.
Stability
As with all linear regulators, the RC5060's linear regulators require a minimum load. With the exception of the 3.3V dual output, however, all of these minimum loads are internal to the RC5060. The 3.3V dual output requires a minimum load of 50mA; if a situation may occur in which the load is less than 50mA, additional steps may be necessary to ensure stability. Furthermore, depending on location, it may be necessary to bypass the drain (or collector) of the linear regulator with a low ESR capacitor for stability. As a rule of thumb, if the pass element is more than 1" from its power source, it should have a bypass.
12
UVLO
If the +5V standby is below approximately 4.5V, the RC5060 will leave off or turn off all outputs. Similar comments apply to the +12V main at 7.5V. The +5V standby UVLO has approximately 0.5V hysteresis, the +12V main UVLO 1V.
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PRODUCT SPECIFICATION
RC5060
Power Good
The Power Good is an open collector that pulls low if any of the outputs are less than 80% of nominal.
Alternate for 2.5V Dual
Instead of the bipolar transistor shown in Figure 4 for Q2, the linear pass element for the 2.5V dual for RAMBUS, a MOSFET and schottky diode can be used as shown in Figure 8.
3.3V Main
Over Temperature
The RC5060 is capable of sourcing substantial current, 200mA minimum to the RAMBUS transistor's base during S0, 144mA to the RAMBUS line during S3, and 100mA to SDRAM during S3. As a result, there can be heavy power dissipation in the IC. While the RC5060 is designed to accept this power dissipation, any overloading of outputs can cause excessive heating. If the RC5060 die temperature exceeds about 150, all outputs are shut off. Outputs remain off until the die temperature returns to its safe area.
RC5060 16 15
2.5V Dual (RAMBUS)
Transistor Selection
External transistor selection depends on usage, differing for the linear regulators and the switches. The MOSFET switches, Ql, Q3, Q5 and Q6 should be sized based on regulation requirements and power dissipation. Since the ATX outputs are 5%, the outputs driven from them must be wider. As an example, if we want to hold 3.3V SDRAM to -10%, we can drop only 5% = 165mV across Q1. At 4.8A, this means Ql must have a maximum RDS,on of 165mV/4.8A = 34m, including tolerance and self-heating effects. We thus choose a Fairchild FDS4410Y, which has 20m maximum RDS, on at 4.5V VGS at 25C. We can estimate power dissipation as (4.8A)2 * 20m = 460mW, which should be acceptable for this package. Similar calculations apply to the other MOSFET switches. Q4 is a MOSFET functioning as a linear regulator. Since it delivers only 500mA, it is easy to select a MOSFET, it need only be able to handle 500mA * (5V5%-3.3V) = 1W. We select the Fairchild FDS6630A in an SO-8 package. Q2 is an NPN bipolar functioning as a linear regulator. As already discussed, it must have a VCE,sat lower than 635mV at IE = 2A and IB = 200mA. Its power dissipation can be as high as (3.3V + 5%-2.5V) * 2A = l.9W.
Figure 8. 2.5V Dual with MOSFET
The schottky should be chosen to have a low Vf at the specified RAMBUS current. The MOSFET's RDS,on must then be lower than (3.3V--5% -2.5V - Vf)/IRAMBUS including temperature. An additional constraint is that the MOSFET must have a gate threshold voltage lower than 1.5V. For example, for 2.8A, choose the diode to be an MBR835, and the MOSFET a Fairchild NDH833N. This same technique can then also be used for RAMBUS currents higher than can be achieved with the bipolar transistor.
Output Capacitor Selection
Output capacitor selection depends on whether the line has overlap time or not. For both the 5V dual and the 2.5V dual, there is guaranteed overlap time between when one source is turned on and the other source turned off. For these outputs, the output capacitor is not needed to hold up the supply, but only for noise filtering and to respond to transient loading. The 3.3V dual and 3.3V SDRAM outputs have deadtime between when one source is turned off and the other source turned on. During the time when both are off, the output current must be supplied by the output capacitor. Mitigating this, it must be realized that the system will be designed in such a way that the current has gone to its sleep value before the transition occurs. For example, the 3.3V dual has a sleep current of 500mA maximum. Maximum deadtime is 6sec, and so charge depletion is 500mA * 6sec = 3C. Suppose that we have a total of 8% drop due to the source tolerance and the MOSFET drop, and we are trying to hold 10% regulation. The remaining 2% = 66mV implies a minimum capacitance of 3C/66mV = 45F.
REV. 1.0.2 9/14/01
13
PRODUCT SPECIFICATION
RC5060
Mechanical Dimensions
20 Lead SOIC
Inches Min. A A1 B C D E e H h L N ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
REV. 1.0.2 9/14/01
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RC5060
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5060M Package 20 pin SOIC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/14/01 0.0m 003 Stock#DS30005060 2000 Fairchild Semiconductor Corporation

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